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v3.0
v2.1
v2.0
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Previous
Version
Changes in Current Version (v4.0)
The core version was changed to v3.3.
The BAR i _PREFETCH parameter description in Table 4-3 · BAR Parameters was expanded to include
the definitions for settings 0 and 1. The BAR i _INITVAL parameter description was updated with further
instructions on setting this parameter.
The “BAR Parameters” section was updated with information on how to configure a DMA_REG_BAR if
a memory or I/O BAR is used for the DMA registers.
In Table 4-4 · Master/DMA Parameters , the DMA_REG_LOC description was updated to note that
BACKEND must be set to 1 for backend access. The DMA_REG_BAR parameter description was
updated to state that the BAR used for DMA registers may not be shared with other memory and I/O
BARs used to access user logic connected to the core.
Table 5-2 · System-Level Signals was updated to revise the description for RST_OUTN. The
CFG_STATUS parameter was added.
The core version was changed to v3.2.
The “Synthesis in Libero IDE” section was added to.
Table 4-1 was updated to include the USE_GLOBAL_TRDY and USE_GLOBAL_IRDY parameters.
Table 4-3 was updated to include the BAR i _64BIT and EXPR_64BIT parameters.
Table 4-5 was updated to include the BAR i _64BIT ( i = 0..9) and EXPR_64BIT parameters.
In Table 5-4 , the BUSY signal description was updated.
The core version was changed to v3.1.
Figure 3-1 was updated.
Table 4-1 and Table 4-5 were updated to include the GENERATE_PCICLK, ONCHIP_ARBITER,
and ONCHIP_IDSEL parameters.
Table 5-1 was updated to change the signal type of SERRN from output to bidirectional.
Table 5-2 was updated to add the CLK_IN, FRAMEN_OUT, IRDYN_OUT, and SERRN_OUT
signals.
The “Clocking” section was added.
v4.0
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